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ADT7316/7317/7318 re v . p r n 02/ 02 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. t el: 781/329-47 0 0 ww w .analog.com fax: 781/326-8703 analog devices, inc., 2 0 0 2 spi/i 2 c ?? ?? ? compatible, 10-bit digital temperature sensor and quad voltage output 12/10/8-bit dac preliminary technical data preliminary technical data features ADT7316 - four 12-bit dacs adt7317 - four 10-bit dacs adt7318 - four 8-bit dacs buffered voltage output guaranteed monotonic by design over all codes 10-bit temperature to digital converter temperature range: -40 o c to +125 o c temperature sensor accuracy of 0.5 o c supply range : + 2.7 v to + 5.5 v dac output range: 0 - 2v ref power-down current 1 ? ? a internal 2.25 v ref option double-buffered input logic buffered / unbuffered reference input option power-on reset to zero volts simultaneous update of outputs ( function) on-chip rail-to-rail output buffer amplifier i 2 c ?? ?? ? , spi tm , qspi tm , microwire tm and dsp-compatible 4- wire serial interface 16-lead qsop package applications portable battery powered instruments personal computers telecommunications systems electronic test equipment domestic appliances process control general description the ADT7316/7317/7318 combines a 10-bit tempera- ture-to-digital converter and a quad 12/10/8-bit dac respectively, in a 16-lead qsop package. this includes a bandgap temperature sensor and a 10-bit adc to monitor and digitize the temperature reading to a resolution of 0.25 o c. the ADT7316/17/18 operates from a single +2.7v to +5.5v supply. the output voltage of the dac ranges from 0 v to 2v ref , with an output voltage settling time of typ 7 msec. the ADT7316/17/18 provides two serial interface options, a four-wire serial interface which is compatible with spi tm , qspi tm , microwire tm and dsp interface standards; and a two-wire i 2 c interface. it features a standby mode that is controlled via the serial interface. the reference for the four dacs is derived either inter- nally or from two reference pins (one per dac pair) .the outputs of all dacs may be updated simultaneously using the software ldac function or external ldac pin. the ADT7316/7317/7318 incorporates a power-on-reset cir- cuit, which ensures that the dac output powers-up to zero volts and it remains there until a valid write takes place. the ADT7316/7317/7318?s wide supply voltage range, low supply current and spi/i 2 c-compatible interface, make it ideal for a variety of applications, including per- sonal computers, office equipment and domestic appli- ances. i 2 c is a registered trademark of philips corporation * protected by u.s. patent no. 5,969,657; other patents pending. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation. functional block diagram v dd va lue register string da c b externa l temperature value register a-to-d converter internal temperature va lue register on-chip tempera ture sensor anal og mu x d i g i t a l m u x limit comparator d i g i t a l m u x dac c registers address pointer register t high limit registers t low limit registers v dd limit registers control c onfig. 1 register control c onfig. 3 register control config. 2 register da c configuration register l da c configuration register interrupt mask registers dac a registers da c b registers dac d registers string dac a string da c c string da c d gain select lo gic power down l ogic v out -a v out -b v out -c v out -d d+ d- smb us/spi interface scl/scl k sda /din dout/add interrup t sta tus registers v dd sensor v dd gnd internal temp sensor v ref -a b v ref -c d ADT7316/17/18 7 8 6 5 4 13 12 11 9 3 14 10 15 16 1 2
?2? rev. prn preliminary technical data ADT7316/adt7317/adt7318-specifications 1 (v dd =2.7 v to 5.5 v, gnd=0 v, ref in =2.25 v, unless otherwise noted) parameter 2 min typ max units cond itions/comments dac dc performance 3,4 adt7318 resolution 8 bits relative accuracy 0.15 1 lsb relative accuracy tbd tbd lsb excluding offset and gain errors differential nonlinearity 0.02 0.25 lsb guaranteed monotonic by design over all codes adt7317 resolution 10 bits relative accuracy 0.5 4 lsb relative accuracy tbd tbd lsb excluding offset and gain errors differential nonlinearity 0.05 0.5 lsb guaranteed monotonic by design over all codes ADT7316 resolution 12 bits relative accuracy 2 16 lsb relative accuracy tbd tbd lsb excluding offset and gain errors differential nonlinearity 0.02 0.9 lsb guaranteed monotonic by design over all codes offset error 0.4 3 % of fsr offset error match 0.5 lsb gain error 0.3 1.25 % of fsr gain error match 0.5 lsb lower deadband 20 60 mv lower deadband exists only if offset error is negative. see figure 5. upper deadband tbd tbd mv upper deadband exists if v ref = v dd and offset plus gain error is positive. see figure 6. offset error drift 6 -12 ppm of fsr/c gain error drift 6 -5 ppm of fsr/c dc power supply rejection ratio 6 -60 db ? v dd = 10% dc crosstalk 6 200 v r l = 2 k ? to gnd or v dd thermal characteristics internal reference used. internal temperature sensor accuracy @ v dd =3.3v 2 c t a = 0c to +85c 3 c t a = -40c to +125c accuracy @ v dd =5v 2 c t a = 0c to +85c 3 c t a = -40c to +125c resolution 10 bits long term drift 0.5 c/1000hrs external temperature sensor external transistor = 2n3906. accuracy @ v dd =3.3v 2 c t a = 0c to +85c. 3 c t a = -40c to +125c accuracy @ v dd =5v 2 c t a = 0c to +85c 3 c t a = -40c to +125c resolution 10 bits update rate, t r t b d s round robin 5 enabled tbd s round robin disabled temperature conversion time tbd s output source current 180 a h igh level 11 a low level voltage output 8-bit dac output resolution 1 c scale factor 8.79 mv/c 0-v ref output. t a = -40c to +125c 17.58 mv/c 0-2v ref output. t a = -40c to +125c 10-bit dac output resolution 0.25 c
ADT7316/7317/7318 ?3? re v . p r n preliminary technical data scale factor 2.2 mv/c 0-v ref output. t a = -40c to +125c 4.39 mv/c 0-2v ref output. t a = -40c to +125c dac erternal reference input 6 v ref input range 1 v dd v buffered reference mode v ref input range 0.25 v dd v unbuffered reference mode v ref input impedance 3 7 4 5 k ? unbuffered reference mode. 0-2 v ref output range. 74 90 k ? unbuffered reference mode. 0- v ref output range. >10 m ? buffered reference mode and power-down mode reference feedthrough -90 d b frequency=10khz channel-tochannel isolation -75 d b frequency=10khz on-chip reference reference voltage 6 2.25 v temperature coefficient 6 80 ppm/ c output characteristics 6 output voltage 7 0.001 v dd -0.001 v this is a measure of the minimum and maximum drive capability of the output amplifier dc output impedance 0.5 ? short circuit current 25 ma v dd = +5v 16 m a v dd = +3v power up time 2.5 s coming out of power down mode. v dd = +5 v 5 s coming out of power down mode. v dd = +3 v digital inputs 6 input current 1 a v in = 0v to v dd v il , input low voltage 0.8 v v dd = +5v10% 0.6 v v dd = +3v10% v ih , input high voltage 1.89 v pin capacitance 3 10 pf all digital inputs scl, sda glitch rejection 50 ns input filtering suppresses noise spikes of less than 50 ns digital output output high voltage, v oh 2.4 v i source = i sink = 200 a output low voltage, v ol 0.4 v i ol = 3 ma output high current, i oh 1mav oh = 5 v output capacitance, c out 50 pf alert output saturation voltage 0.8 v i out = 4 ma i 2 c timing characteristics 8,9 serial clock period, t 1 2.5 s fast-mode i 2 c. see figure 1 data in setup time to scl high, t 2 data out stable after scl low, t 3 0 ns see figure 1 sda low setup time to scl low (start condition), t 4 50 ns see figure 1 sda high hold time after scl high (stop condition), t 5 50 ns see figure 1 sda and scl fall time, t 6 90 ns see figure 1 spi timing characteristics 10, 11 to sclk setup time, t 1 0 ns see figure 2 sclk high pulsewidth, t 2 50 ns see figure 2 sclk low pulse, t 3 50 ns see figure 2 data access time after sclk falling edge, t 4 12 35 ns see figure 2 data setup time prior to sclk rising edge, t 5 20 ns see figure 2 data hold time after sclk rising edge, t 6 0 ns see figure 2 to sclk hold time, t 7 0 ns see figure 2 to dout high impedance, t 8 40 ns see figure 2 power requirements v dd 2.7 5.5 v v dd settling time 50 ms v dd settles to within 10% of it?s final voltage level. parameter 2 min typ max units cond itions/comments
?4? r e v . p r n preliminary technical data ADT7316/7317/7318 dac ac characteristics 1 (v dd = +2.7v to +5.5 v; r l =4k7 ? to gnd; c l =200pf to gnd; 4k7 ? to v dd ; all specifications t min to t max unless otherwise noted.) parameter 2 min typ @ 25c m a x units cond itions/comments output voltage settling time v ref =v dd =+5v adt7318 6 8 s 1/4 scale to 3/4 scale change (40 hex to c0 hex) adt7317 7 9 s 1/4 scale to 3/4 scale change (100 hex to 300 hex) ADT7316 8 10 s 1/4 scale to 3/4 scale change (400 hex to c00 hex) slew rate 0.7 v/s major-code change glitch energy 12 nv-s 1 lsb change around major carry. digital feedthrough 0.5 nv-s digital crosstalk 1 nv-s analog crosstalk 0.5 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 200 khz v ref =2v0.1vpp total harmonic distortion -70 d b v ref =2.5v0.1vpp. frequency=10khz. notes 1 guaranteed by design and characterization, not production tested 2 see terminology specifications subject to change without notice. t 1 t 4 t 2 t 3 t 5 scl sda data in sda data out figure 1. diagram for i 2 c bus timing i dd (normal mode) 13 0.85 1.3 ma v ih = v dd and v il = gnd i dd (power down mode) 1 3 a v dd = +4.5v to +5.5v, v ih =v dd and v il =gnd 0.5 1 a v dd = +2.7v to +3.6v, v ih =v dd and v il =gnd power dissipation tbd tbd tbd w v dd = +2.7 v. using normal mode tbd tbd tbd w v dd = +2.7 v. using shutdown mode notes: 1 temperature ranges are as follows: a version: -40c to +125c. 2 see terminology. 3 dc specifications tested with the outputs unloaded. 4 linearity is tested using a reduced code range:; ADT7316 (code 115 to 4095); adt7317 (code 28 to 1023); adt7318 (code 8 to 255) 5 see terminology. 6 guaranteed by design and characterization, not production tested 7 in order for the amplifier output to reach its minimum voltage, offset error must be negative. in order for the amplifier output to reach its maximum voltage, v ref =v dd , "offset plus gain" error must be positive. 8 the sda & scl timing is measured with the input filters turned on so as to meet the fast-mode i 2 c specification. switching off the input filters improves the transfer rate but has a negative affect on the emc behaviour of the part. 9 guaranteed by design. not tested in production. 10 guaranteed by design and characterization, not production tested. 11 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 12 measured with the load circuit of figure 3. 13 i dd spec. is valid for all dac codes. interface inactive. all dacs active. load currents excluded. specifications subject to change without notice.
ADT7316/7317/7318 ? 5 ? re v . p r n preliminary technical data figure 3. load circuit for access time and bus relinquish time 1.6v i ol 200 a 200 a i ol to output pin c l 50pf figure 2. diagram for spi bus timing dout dbx dbx d bx db7 sclk 1 2 3 4 8 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 din db7 db6 d b0 db8 msb l sb msb msb v dd 47? 47? 200 pf to da c ou tp ut figure 4. load circuit for dac outputs
? 6 ? re v . p r n preliminary technical data ADT7316/7317/7318 absolute maximum ratings* v dd to gnd ?0.3 v to +7 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v digital output voltage to gnd ?0.3 v to v dd + 0.3 v reference input voltage to gnd ?0.3 v to v dd + 0.3v operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature +150c 16-lead qsop package power dissipation (t j max - t a ) / ja ja thermal impedance 150 c/w (qsop) reflow soldering peak temperature +220 +/- 0c time of peak temperature 10 sec to 40 sec * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide model temperature range dac resolution package description package options adt7318arq ?40c to +125c 8-bits 16-lead qsop rq-16 adt7317arq -40c to +125c 10-bits 16-lead qsop rq-16 ADT7316arq -40c to +125c 12-bits 16-lead qsop rq-16 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADT7316/7317/7318 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin configuration qsop table 1. i 2 c address selection add pin i 2 c address low 1001 000 float 1001 010 high 1001 011 a dt7316/ 7317/7318 to p view (not to scale) interrupt v out -a v out -b gnd sda/din dout/add vdd d+ d- scl/sclk v out -c 1
v out -d v ref -ab v ref -cd
ADT7316/7317/7318 ? 7 ? re v . p r n preliminary technical data

1v out b buffered analog output voltage from dac b. the output amplifier has rail-to-rail operation. 2v out a buffered analog output voltage from dac a. the output amplifier has rail-to-rail operation. 3v ref ab reference input pin for dacs a and b.it may be configured as a buffered or unbuffered input to each or both of the dacs a and b. it has an input range from 0.25 v to v dd in unbuffered mode and from 1 v to v dd in buffered mode. 4 spi active low control input. this is the frame synchronization signal for the input data. when cs goes low, it enables the input register and data is transferred in and out on the ris- ing edges of the following serial clocks. this pin must be kept high for i 2 c mode of operation. is also used as a control pin when selecting the serial interface type after power-up. 5 g n d ground reference point for all circuitry on the part. analog and digital ground. 6v dd positive supply voltage, +2.7 v to +5.5 v.the supply should be decoupled to ground. 7 d + positive connection to external temperature sensor 8 d - negative connection to external temperature sensor 9 active low control input that transfers the contents of the input registers to their respective dac registers. pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows simultaneous update of all dac outputs. bit c3 of con- trol configuration 3 register enables pin. default is with pin controlling the loading of dac registers. 10 interrupt o ver limit interrupt. the output polarity of this pin can be set to give an active low or active high interrupt when temperature, v dd and ain limits are exceeded. default is active low. 11 dout/add spi serial data output. logic output. data is clocked out of any register at this pin. data is clocked out at the falling edge of sclk. add, i 2 c serial bus address selection pin. logic input. during the first valid i 2 c bus commu- nication this pin is checked to determine the serial bus address assigned to the ADT7316/17/ 18. any subsequent changes on this pin will have no affect on the i 2 c serial bus address. a low on this pin gives the address 1001 000, leaving it floating gives the address 1001 010 and set- ting it high gives the address 1001 011. 12 sda/din sda - i 2 c serial data input. i 2 c serial data to be loaded into the parts registers is provided on this input. din - spi serial data input. serial data to be loaded into the parts registers is provided on this input. data is clocked into a register on the rising edge of sclk. 13 scl/sclk s erial clock input. this is the clock input for the serial port. the serial clock is used to clock data out of any register of the ADT7316/7317/7318 and also to clock data into any register that can be written to. 14 v ref cd reference input pin for dacs c and d.it may be configured as a buffered or unbuffered input to each or both of the dacs c and d. it has an input range from 0.25 v to v dd in unbuffered mode and from 1 v to v dd in buffered mode. 15 v out d buffered analog output voltage from dac d. the output amplifier has rail-to-rail operation. 16 v out c buffered analog output voltage from dac c. the output amplifier has rail-to-rail operation.
? 8 ? re v . p r n preliminary technical data ADT7316/7317/7318 terminology relative accuracy relative accuracy or integral nonlinearity (inl) is a mea- sure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. typical inl versus code plots can be seen in tpcs 1, 2, and 3. differential nonlinearity differential nonlinearity (dnl) is the difference be- tween the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac and temperature sensor adc is guaranteed monotonic by design. typical dac dnl versus code plots can be seen in tpcs 4, 5, and 6. offset error this is a measure of the offset error of the dac and the output amplifier. (see figures 5 and 6.) it can be negative or positive. it is expressed in mv. offset error match this is the difference in offset error between any two channels. gain error this is a measure of the span error of the dac. it is the deviation in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. gain error match this is the difference in gain error between any two channels. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full- scale range)/ c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full- scale range)/ c. dc power-supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the s upply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in dbs. v ref is held at 2 v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac while monitoring another dac. it is expressed in v. reference feedthrough this is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated (i.e., is high). it is expressed in dbs. channel-to-channel isolation this is the ratio of the amplitude of the signal at the out- put of one dac to a sine wave on the reference input of another dac. it is measured in dbs. major-code transition glitch energy major- code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv secs and is measured when the digital code is changed by 1 lsb at the major carry transi- tion (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital input pins of the device but is measured when the dac is not being written to the. it is specified in nv secs and is mea- sured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s or vice versa. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in stand-alone mode and is expressed in nv secs. analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by l oading one of the input registers with a full- scale code change ( all 0s to all 1s and vice versa) while keeping high. then pulse low and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv secs. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent out- put change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with low and monitoring the output of another dac. the energy of the glitch is expressed in nv secs. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying band- width is the frequency at which the output amplitude falls to 3 db below the input.
ADT7316/7317/7318 ? 9 ? re v . p r n preliminary technical data gain error + offset error output voltage negative offset error dac c ode negative offset error a m pl ifier footroom lower deadband codes actual ideal output vol tage positive offset error dac code gain error + offset error actual ideal upper deadband codes full scale figure 5. transfer function with negative offset figure 6. transfer function with positive offset (v ref = v dd ) total harmonic distortion this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in dbs. round robin this term is used to describe the ADT7316/17/18 cycling through the available measurement channels in sequence taking a measurement on each channel.
? 10 ? re v . p r n preliminary technical data ADT7316/7317/7318 code i n l e r r o r - l s b s 1.0 0.5 -1.0 050 250 100 150 200 0 -0.5 t a =25 c v dd =5v tpc 1. adt7318 typical inl plot tpc 2. adt7317 typical inl plot tpc 3. ADT7316 typical inl plot code i n l e r r o r - l s b s 12 0 -4 -8 8 4 04000 1000 2000 3000 -12 t a =25 c v dd =5v code i n l e r r o r - l s b s 3 0 200 1000 400 600 800 0 -1 -2 -3 2 1 t a =25 c v dd =5v code d n l e r r o r - l s b s 0.4 -0.4 600400 800 100 0 0 -0.6 0.6 0.2 -0.2 t a =25 c v dd =5v 200 0 code d n l e r r o r - l s b s 050 25 100 150 200 -0. 1 -0. 2 -0. 3 0. 3 0. 1 0. 2 0 t a =25 c v dd =5v tpc 4. adt7318 typical dnl plot tpc 5. adt7317 typical dnl plot tpc 6. ADT7316 typical dnl plot v ref -v e r r o r - l s b s 0.5 0. 25 -0.5 01 5 234 0 -0.25 v dd =5v t a =25 c max inl max dnl min dnl min inl temperature - c e r r o r - l s b s 0.5 0.2 -0.5 40 0 40 0 -0.2 v dd =5v v ref =3v max inl 80 120 -0.4 -0.3 -0.1 0.1 0.3 0.4 max dnl min inl min dnl gain error temperature - c e r r o r - % f s r 1 0.5 -1 40 0 40 0 -0.5 v dd =5v v ref =2v offset error 80 120 tpc 7. adt7318 inl and dnl error vs v ref tpc 8. adt7318 inl error and dnl error vs temperature tpc 9. adt7318 offset error and gain error vs temperature code d n l e r r o r - l s b s 0.5 2000 3000 4000 0 -1 1 -0.5 t a =25 c v dd =5v 1000 0
ADT7316/7317/7318 ? 11 ? re v . p r n preliminary technical data gain error v dd -volts e r r o r - % f s r 0.2 -0.6 01 3 0 -0.4 t a =25 c v ref =2v 46 -0.5 -0.3 -0.2 -0.1 0.1 25 offset error tpc 10. offset error and gain error vs v dd 5v source sink/source current - ma v o u t - v o l t s 5 0 01 3 4 46 1 2 3 25 3v source 3v sink 5v sink tpc 11. v out source and sink current capability code i d d - a 600 zero-scale full-scal e 500 400 300 200 100 0 t a =25 c v dd =5v v ref =2v tpc 12. supply current vs. dac code v dd -volts i d d - a 600 2.5 500 400 300 200 100 0 3.0 3 .5 4.0 4 .5 5.0 5.5 -40 c +25 c +105 c tpc 13. supply current vs. supply volt- age v dd -volts i d d - a 0.5 0 0.4 0.1 0.2 0.3 2.5 3. 0 4.0 4.5 5.53.5 5. 0 +105 c -40 c +25 c tpc 14. power-down current vs. supply voltage v out a 5 s ch1 ch2 sclk t a =25 c v dd =5v v ref =5v ch1 1v, ch2 5v, time base= 1 s/div tpc 15. half-scale settling (1/4 to 3/4 scale code change) t a =25 c v dd =5v v ref =2v ch1 ch2 ch1 500mv, ch2 5.00v, time base = 1 s/div v out a tpc 16. exiting power-down to midscale 1 s/div 2.4 8 2.49 v o u t - v o l t s 2.47 2.50 tpc 17. ADT7316 major-code transition glitch energy frequency - khz 10 -40 0.01 -20 -30 0 -10 d b 0.1 1 10 100 1 k 10k -50 -60 tpc 18. multiplying bandwidth (small- signal frequency response)
? 12 ? re v . p r n preliminary technical data ADT7316/7317/7318 v dd =5v t a =25 c v ref -volts f u l l - s c a l e e r r o r - v o l t s 0.02 -0.02 01 3 0.01 -0.01 46 0 25 tpc 19. full-scale error vs. v ref 150ns/div 1 m v / d i v tpc 20. dac-to-dac crosstalk tpc 21. psrr vs supply ripple frequency title 0 0 0 00 0 t i t l e 0000

tpc 22. temperature error @ 3.3 v and 5.5 v
ADT7316/7317/7318 ? 13 ? re v . p r n preliminary technical data functional description - dac the ADT7316/7317/7318 has quad resistor-string dacs fabricated on a cmos process with a resolutions of 12, 10 and 8 bits respectively. they contain four output buffer amplifiers and is written to via i 2 c serial interface or spi serial interface. see serial interface selection section for more information. the ADT7316/7317/7318 operates from a single supply of 2.7 v to 5.5 v and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7v/ s. dacs a and b share a common reference input, namely v ref ab. dacs c and d share a common reference input, namely v ref cd. each reference input may be buffered to draw virtually no current from the reference source, or unbuffered to give a reference input range from gnd to v dd . the devices have a power-down mode, in which all dacs may be turned off completely with a high-imped- ance output. each dac output will not be updated until it receives the ldac command. therefore while the dac registers would have been written to with a new value, this value will not be represented by a voltage output until the dacs have received the ldac command. reading back from any dac register prior to issuing an ldac command will result in the digital value that corresponds to the dac output voltage. thus the digital value written to the dac register cannot be read back until after the ldac command has been initiated. this ldac command can be given by either pulling the pin low, setting up bits d4 and d5 of dac configuration register(address = 1bh) or using the ldac register(address = 1ch). digital-to-analog section the architecture of one dac channel consists of a resis- tor-string dac followed by an output buffer amplifier. the voltage at the v ref pin or the on-chip reference of 2.25 v provides the reference voltage for the correspond- ing dac. figure 7 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by: v ref * d v out = ---------- 2 n where d=decimal equivalent of the binary code which is loaded to the dac register; 0-255 for adt7318 (8-bits) 0-1023 for adt7317 (10-bits) 0-4095 for ADT7316 (12-bits) n = dac resolution. v ref ab int v ref reference buffer buf ga in m ode (gain=1 or 2) v out a outp ut b uffer amplifier resistor string dac register inp ut register figure 7. single dac channel architecture resistor string the resistor string section is shown in figure 9. it is sim- ply a string of resistors, each of value r. the digital code loaded to the dac register determines at what node on the string the voltage is tapped off to be fed into the out- put amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. be- cause it is a string of resistors, it is guaranteed monotonic. dac reference inputs there is a reference pin for each pair of dacs. the refer- ence inputs are buffered but can also be individually con- figured as unbuffered. 2.25 v internal v ref string dac a string dac b v re f -ab figure 8. dac reference buffer circuit the advantage with the buffered input is the high imped- ance it presents to the voltage source driving it. however if the unbuffered mode is used, the user can have a refer- ence voltage as low as 0.25 v and as high as v dd since there is no restriction due to headroom and footroom of the reference amplifier.
? 14 ? re v . p r n preliminary technical data ADT7316/7317/7318

figure 9. resistor string if there is a buffered reference in the circuit , there is no need to use the on-chip buffers. in unbuffered mode the input impedance is still large at typically 90 k ? per refer- ence input for 0-v ref output mode and 45 k ? for 0-2v ref output mode. the buffered/unbuffered option is controlled by the dac configuration register (address 1bh, see data register descriptions). the ldac configuration register controls the option to select between internal and external voltage references. the default setting is for external reference selected. output amplifier the output buffer amplifier is capable of generating out- put voltages to within 1mv of either rail. its actual range depends on the value of v ref , gain and offset error. if a gain of 1 is selected (bits 0-3 of dac configuration register = 0) the output range is 0.001 v to v ref . if a gain of 2 is selected (bits 0-3 of dac configuration register = 1) the output range is 0.001 v to 2v ref . how- ever because of clamping the maximum output is limited to v dd - 0.001v. the output amplifier is capable of driving a load of 2k ? to gnd or v dd, in parallel with 500pf to gnd or v dd . the source and sink capabilities of the output amplifier can be seen in the plot in tpc 11. the slew rate is 0.7v/ s with a half-scale settling time to +/-0.5 lsb (at 8 bits) of 6 s. functional description power-up time on power-up it is important that no communication to the part is initiated until 200ms after vcc has settled. during this 200ms the part is performing a calibration routine and any communication to the device will interrupt this rou- tine and could cause erroneous temperature measurements. v dd must have settled to within 10% of it ? s final value after 50ms power-on time has elasped. therefore once power is applied to the ADT7316/17/18, it can be ad- dressed 250ms later. if it not possible to have v dd at it ? s nominal value by the time 50ms has elasped then it is recommended that a measurement be taken on the v dd channel before a temperature measurement is taken. temperature sensor the ADT7316/7317/7318 contains a two-channel a to d converter with special input signal conditioning to enable operation with external and on-chip diode temperature sensors. when the ADT7316/7317/7318 is operating nor- mally, the a to d converter operates in a free-running mode. when in round robin mode the analog input mul- tiplexer sequently selects the v dd input channel, on-chip temperature sensor to measure its internal temperature and then the external temperature sensor. these signals are digitized by the adc and the results stored in the various value registers. the measured results are compared with the internal and external, t high , t low limits. these temperature limits are stored in on-chip registers. if the temperature limits are not masked out then any out of limit comparisons generate flags that are stored in interrupt status 1 register and one or more out-of limit results will cause the interrupt output to pull either high or low depending on the output polarity setting. theoretically, the temperature sensor and adc can mea- sure temperatures from -128 o c to +127 o c with a resolu- tion of 0.25 o c. however, temperatures outside t a are outside the guaranteed operating temperature range of the device. temperature measurement from -128 o c to +127 o c is possible using an external sensor. temperature measurement is initiated by three methods. the first method is applicable when the part is in single channel measurement mode. it uses an internal clock countdown of 20ms and then a conversion is preformed. the internal oscillator is the only circuit that ? s powered up between conversions and once it times out, every 20ms, a wake-up signal is sent to power-up the rest of the cir- cuitry. a monostable is activated at the beginning of the wake-up signal to ensure that sufficient time is given to the power-up process. the monostable typically takes 4 s to time out. it then takes typically 25s for each conver- sion to be completed. the temperature is measured 16 times and internally averaged to reduce noise. the total time to measure a temperature channel is typically 400us (25us x 16). the new temperature value is loaded into the temperature value register and ready for reading by the i 2 c or spi interface. the user has the option of disabling the averaging by setting a bit (bit 5) in the control con- figuration register 2 (address 19h). the ADT7316/7317/ 7318 defaults on power-up with the averaging enabled. temperature measurement is also initiated after every read or write to the part when the part is in single channel mea- surement mode. once serial communication has started, any conversion in progress is stopped and the adc reset. conversion will start again immediately after the serial communication has finished. the temperature measure- ment proceeds normally as described above. the third method is applicable when the part is in round robin measurement mode. the part measures both the
ADT7316/7317/7318 ? 15 ? re v . p r n preliminary technical data internal and external temperature sensors as it cycles through all possible measurement channels. the two tem- perature channels are measured each time the part runs a round robin sequence. in round robin mode the part is continously measuring. v dd monitoring the ADT7316/17/18 also has the capability of monitoring it ? s own power supply. the part measures the voltage on it ? s v dd pin to a resolution of 10 bits. the resultant value is stored in two 8-bit registers, the two lsbs stored in register address 03h and the eight msbs are stored in register address 06h. this allows the user to have the op- tion of just doing a one byte read if 10-bit resolution is not important. the measured result is compared with v high and v low limits. if the v dd interrupt is not masked out then any out of limit comparison generates a flag in inter- rupt status 2 register and one or more out-of-limit results will cause the interrupt output to pull either high or low depending on the output polarity setting. measuring the voltage on the v dd pin is regarded as moni- toring a channel. therefore, along with the internal and external temperature sensors the v dd voltage makes up the third and final monitoring channel. you can select the v dd channel for single channel measurement by setting bit c4 = 1 and setting bit 0 to bit 2 to all 0 ? s in control configuration 2 register. when measuring the v dd value the reference for the adc is sourced from the internal reference. table 2 shows the data format. as the max v cc voltage measurable is 7 v, internal scaling is performed on the v cc voltage to match the 2.25v internal reference value. below is an example of how the transfer function works. v dd = 5 v adc reference = 2.25 v 1 lsb = adc reference / 2^10 = 2.25 / 1024 = 2.197mv scale factor = fullscale v cc / adc reference = 7 / 2.25 = 3.11 conversion result = v dd / ((7/scale factor) x lsb size) = 5 / (3.11 x 2.197mv) = 2dbh table 2. v dd data format, v ref = 2.25v v dd value digital output binary hex 2.5 v 01 0110 1110 16e 3 v 01 1011 0111 1b7 3.5 v 10 0000 0000 200 4 v 10 0100 1001 249 4.5 v 10 1001 0010 292 5 v 10 1101 1011 2db 5.5 v 11 0010 0100 324 6 v 11 0110 1101 36d 6.5 v 11 1011 0110 3b6 7 v 11 1111 1111 3 f f on-chip reference the ADT7316/17/18 has an on-chip 1.2 v band-gap refernece which is gained up by a switched capacitor am- plifier to give an output of 2.25 v. the amplifier is only powered up at the start of the conversion phase and is powered down at the end of conversion. on power-up the default mode is to have the internal reference selected as the reference for the dac and adc. the internal refer- ence is always used when measuring the internal and ex- ternal temperature sensors. round robin measurement on power-up the ADT7316/17/18 goes into round robin mode but monitoring is disabled. setting bit c0 of con- figuration register 1 to a 1 enables conversions. it se- quences through the three channels of v dd , internal temperature sensor and external temperature sensor and takes a measurement from each. at intervals of tbd ms another measurement cycle is performed on all three chan- nels. this method of taking a measurement on all three channels in one cycle is called round robin. setting bit 4 of control configuration 2 (address 19h) disables the round robin mode and in turn sets up the single channel mode. the single channel mode is where only one chan- nel, eg. internal temperature sensor, is measured in each conversion cycle. the time taken to monitor all channels will normally not be of interest, as the most recently measured value can be read at any time. for applications where the round robin time is impor- tant, it can be easily calculated. as mentioned previously a conversion on each temperature channel takes 25 us and on the v dd channel it takes 15 us. each channel is measured 16 times and internally aver- aged to reduce noise. the total cycle time for voltage and temperature channels is therefore nominally : (2 x 16 x 25) + (16 x 15) = 1.04 ms single channel measurement setting c4 of control configuration 2 register enables the single channel mode and allows the ADT7316/17/18 to focus on one channel only. a channel is selected by writ- ing to bits 0:2 in register control configuration 2 regis- ter. for example, to select the v dd channel for monitoring write to the control configuration 2 register and set c4 to 1 (if not done so already), then write all 0 ? s to bits 0 to 2 . all subsequent conversions will be done on the v dd channel only. to change the channel selection to the in- ternal temperature channel, write to the control configu- ration 2 register and set c0 = 1. when measuring in single channel mode there is a time delay of tbd us be- tween each measurement. a measurement is also initiated after every read or write operation.
? 16 ? re v . p r n preliminary technical data ADT7316/7317/7318 measurement method internal temperature measurement the ADT7316/7317/7318 contains an on-chip bandgap temperature sensor, whose output is digitized by the on- chip adc. the temperature data is stored in the internal temperature value register. as both positive and nega- tive temperatures can be measured, the temperature data is stored in two's complement format, as shown in table 3 . the thermal characteristics of the measurement sensor could change and therefore an offset is added to the mea- sured value to enable the transfer function to match the thermal characteristics. this offset is added before the temperature data is stored. the offset value used is stored in the internal temperature offset register. external temperature measurement the ADT7316/7317/7318 can measure the temperature of one external diode sensor or diode-connected transistor. the forward voltage of a diode or diode-connected tran- sistor, operated at a constant current, exhibits a negative temperature coefficient of about -2mv/ o c. unfortunately, the absolute value of v be , varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass-production. the time taken to measure the external temperature can be reduced by setting c0 of control config. 3 register (1ah). this increases the adc clock speed from 1.4khz to 22khz but the analog filters on the d+ and d- input pins are switched off to accommodate the higher clock speeds. running at the slower adc speed, the time taken to measure the external temperature is tbd while on the fast adc this time is reduced to tbd. the technique used in the ADT7316/7317/7318 is to measure the change in v be when the device is operated at two different currents. this is given by: ? v be = kt/q x ln(n) where: k is boltzmann ? s constant q is charge on the carrier t is absolute temperature in kelvins n is ratio of the two currents figure 10 shows the input signal conditioning used to measure the output of an external temperature sensor. this figure shows the external sensor as a substrate tran- sistor, provided for temperature monitoring on some mi- croprocessors, but it could equally well be a discrete transistor. if a discrete transistor is used, the collector will not be grounded, and should be linked to the base. if a pnp transistor is used the base is connected to the d- input and the emitter to the d+ input. if an npn transistor is used, the emitter is connected to the d- input and the base to the d+ input. we recommend that a 2n3906 be used as the external transistor. to prevent ground noise interfering with the measure- ment, the more negative terminal of the sensor is not ref- erenced to ground, but is biased above ground by an internal diode at the d- input. as the sensor is operating in a noisy environment, c1 is provided as a noise filter. see the section on layout considerations for more informa- tion on c1. to measure ? v be , the sensor is switched between operating currents of i and n x i. the resulting waveform is passed through a lowpass filter to remove noise, thence to a chop- per-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to ? v be . this voltage is mea- sured by the adc to give a temperature output in 8-bit two ? s complement format. to further reduce the effects of noise, digital filtering is performed by averaging the re- sults of 16 measurement cycles. figure 10. signal conditioning for external diode temperature sensors v dd i nxi i bias d+ d- remote sensing tr ansis t or (2n3906) lowpas s f ilter f c = 65khz to ad c v out+ v out- bias diode c1 optional capacitor, up to 3nf max. can be added to improve high frequency noise rejection in noisy environments
ADT7316/7317/7318 ? 17 ? re v . p r n preliminary technical data layout considerations digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. the following precautions should be taken: 1. place the ADT7316/17/18 as close as possible to the remote sensing diode. provided that the worst noise sources such as clock generators, data/address buses and crts are avoided, this distance can be 4 to 8 inches. 2. route the d+ and d- tracks close together, in parallel, with grounded guard tracks on each side. provide a ground plane under the tracks if possible. 3. use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended. gnd d+ d- gnd 10 mil. 10 mil. 10 mil. 10 mil. 10 mil. 10 mil. 10 mil. figure 12. arrangement of signal tracks 4. try to minimize the number of copper/solder joints, which can cause thermocouple effects. where copper/ solder joints are used, make sure that they are in both the d+ and d- path and at the same temperature. thermocouple effects should not be a major problem as 1 o c corresponds to about 240v, and thermocouple voltages are about 3v/ o c of temperature difference. unless there are two thermocouples with a big tempera- ture differential between them, thermocouple voltages should be much less than 200mv. 5. place 0.1f bypass and 2200pf input filter capacitors close to the ADT7316/17/18. 6. if the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. this will work up to about 6 to 12 feet. 7. for really long distances (up to 100 feet) use shielded twisted pair such as belden #8451 microphone cable. connect the twisted pair to d+ and d- and the shield to gnd close to the ADT7316/17/18. leave the re- mote end of the shield unconnected to avoid ground loops. because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. when using long cables, the filter ca- pacitor may be reduced or removed. cable resistance can also introduce errors. 1 series resis- tance introduces about 0.5 o c error. temperature value format one lsb of the adc corresponds to 0.25 c. the adc can theoretically measure a temperature span of 255 c. the internal temperature sensor is guaranteed to a low value limit of -40 c. it is possible to measure the full temperature span using the external temperature sensor. the temperature data format is shown in tables 3. the result of the internal or external temperature mea- surements is stored in the temperature value registers, and is compared with limits programmed into the internal or external high and low registers. table 3. temperature data format (internal and ex- ternal temperature) temperature d igital output db9..........db0 -40 c 11 0110 0000 nxi i v dd i bias to a d c v out+ v out- bias diode internal sense tra nsis t or figure 11. top level structure of internal temperature sensor
? 18 ? re v . p r n preliminary technical data ADT7316/7317/7318 -25 c 11 1001 1100 -10 c 11 1101 1000 -0.25 c 11 1111 1111 0 c 00 0000 0000 +0.25 c 00 0000 0001 +10 c 00 0010 1000 +25 c 00 0110 0100 +50 c 00 1100 1000 +75 c 01 0010 1100 +100 c 01 1001 0000 +105 c 01 1010 0100 +125 c 01 1111 0100 temperature conversion formula: 1. positive temperature = adc code/4 2. negative temperature = (adc code* - 512)/4 *db9 is removed from the adc code interrupts the measured results from the inetrnal temperature sen- sor, external temperature sensor and the v dd pin are com- pared with the t high /v high and t low /v low limits. these limits are stored in on-chip registers. please note that the limit registers are 8 bits long while the conversion results are 10 bits long. if the limits are not masked out then any out of limit comparisons generate flags that are stored in interrupt status 1 register (address = 00h) and interrupt status 2 register (address = 01h). one or more out-of limit results will cause the interrupt output to pull either high or low depending on the output polarity set- ting. figure 13 shows the interrupt structure for the ADT7316/ 17/18. it gives a block diagram representation of how the various measurement channels affect the interrupt pin. thermal voltage output the ADT7316/17/18 has the capability of outputting a voltage that is proportional to temperature. dac a output can be configured to reperesent the temperature of the internal sensor while dac b output can be configured to reperesent the external temperature sensor. bits 5 and 6 of control configuration 3 register select the temperature proportional output voltage. each time a temperature measurement is taken the dac output is updated. the output resolution adt7318 is 8 bits with 1 c change corresponding to one lsb change. the output resolution for the ADT7316 and adt7317 is capable of 10 bits with 0.25 c change corresponding to one lsb change. the default output resolution for the ADT7316 and adt7317 is 8 bits. to increase this to 10 bits, set bit 1=1 of con- trol configuration 3 register. the default output range is 0v-v ref and this can be increased to 0v-2v ref . increasing the outout voltage span to 2v ref can be done by setting d0 = 1 for dac a (internal temperature sensor) and d1 = 1 for dac b (external temperature sensor) in dac configuration register (address 1bh). the output voltage is capable of tracking a max tempera- ture range of -128 c to +127 c but the default setting is - 40 c to +127 c. if the output voltage range is 0v-v ref control configuration register 1 interrupt mask registers s t a t u s b i t s int err upt status register 1 (temp and ext. diod e check) watchdog limit compa risons external tem p v dd diode fault interrupt enable bit interrupt (latched output ) read reset s/w reset s t a t u s b i t interrupt st at us register 2 (v dd ) internal temp figure 13. ADT7316/17/18 interrupt structure
ADT7316/7317/7318 ? 19 ? re v . p r n preliminary technical data (v ref = 2.25 v) then this corresponds to 0v representing - 40 c and 1.48v representing +127 c. this of course will give an upper deadband between 1.48v and v ref . the internal and external analog temperature offset registers can be used to vary this upper deadband and con- sequently the temperature that 0v corresponds to. tables 4 and 5 give examples of how this is done using a dac output voltage span of v ref and 2v ref respectivily. simply write in the temperature value, in 2 ? s complement format, that you want 0v to start at. for example, if you are using the dac a output and you want 0v to start at -40 c then program d8h into the internal analog temperature off- set register (address 21h). this is an 8-bit register and thus only has a temperature offset resolution of 1 c for all device models. use the following formulas to determine the value to program into the offset registers. negative temperatures : - offset register code(d)* = (0v temp) + 128 *d7 of offset register code is set to 1 for negative temperatures. example : - offset register code(d) = (-40) + 128 = 88d = 58h since a negative temperature has been inputted into the equation, db7 (msb) of the offset register code is set to a 1. therefore 58h becomes d8h. 58h + db7(1) ? d8h positive temperatures : - offset register code(d) = 0v temp example : - offset register code (d) = 10d = 0ah table 4. thermal voltage output (0v-v ref ) o/p voltage default c max c sample c 0v -40 -128 0 0.5v +17 -71 +56 1v +73 -15 +113 1.12v +87 -1 +127 1.47v +127 +39 udb* 1.5v udb* +42 udb* 2v udb* +99 udb* 2.25v udb* +127 udb* * upper deadband has been reached. dac output is not capable of increasing. reference figure 6. table 5. thermal voltage output, (0v-2v ref ) o/p voltage default c max c sample c 0v -40 -128 0 0.25v -26 -114 14 0.5v +12 -100 +28 0.75v +3 -85 43 1v +17 -71 +57 1.12v +23 -65 +63 1.47v +43 -45 +83 1.5v +45 -43 +85 2v +73 -15 +113 2.25v +88 0 +127 2.5v +102 +14 udb* 2.75v +116 +28 udb* 3v udb* +42 udb* 3.25v udb* +56 udb* 3.5v udb* +70 udb* 3.75v udb* +85 udb* 4v udb* +99 udb* 4.25v udb* +113 udb* 4.5v udb* +127 udb* * upper deadband has been reached. dac output is not capable of increasing. reference figure 6. the following equation is used to work out the various temperatures for the corresponding 8-bit dac output :- 8-bit temp = (dac o/p 1 lsb) + ( 0v temp) for example, if the output is 1.5v, v ref = 2.25 v, 8-bit dac has an lsb size = 2.25v/255 = 8.82x10 -3 , and 0v temp is at -128 c then the resultant temperature works out to be :- (1.5 8.82x10 -3 ) + (-128) = +42 c the following equation is used to work out the various temperatures for the corresponding 10-bit dac output :- 10-bit temp = ((dac o/p 1 lsb)x0.25) + ( 0v temp) for example, if the output is 0.4991v, v ref = 2.25 v, 10- bit dac has an lsb size = 2.25v/1024 = 2.197x10 -3 , and 0v temp is at -40 c then the resultant temperature works out to be :- ((0.4991 2.197x10 -3 )x0.25) + (-40) = +16.75 c figure 14 shows a graph of dac output vs temperature for a v ref = 2.25 v.
? 20 ? re v . p r n preliminary technical data ADT7316/7317/7318

figure 14. dac output vs temperature, v ref = 2.25 v ADT7316/7317/7318 registers the ADT7316/17/18 contains registers that are used to store the results of external and internal temperature mea- surements, v dd value measurements, high and low tem- perature and supply voltage limits, set output dac voltage levels, configure multipurpose pins and generally control the device. a description of these registers follows. the register map is divided into registers of 8-bits long. each register has it ? s own indvidual address but some consist of data that is linked with other registers. these registers hold the 10-bit conversion results of measure- ments taken on the temperature and v dd channels. for example, the 8 msbs of the v dd measurement are stored in register address 06h while the 2 lsbs are stored in register address 03h. the link involved between these types of registers is that when the lsb register is read first then the msb registers associated with that lsb register are locked to prevent any updates. to unlock these msb registers the user has only to read any one of them, which will have the affect of unlocking all previously locked msb registers. so for the example given above if register 03h was read first then msb registers 06h and 07h would be locked to prevent any updates to them. if register 06h was read then this register and register 07h would be sub- sequently unlocked. 1st read command lsb register output data lock associated msb registers figure 15. phase 1 of 10-bit read 2nd read command msb register output data unlock a ssociated msb registers figure 16. phase 2 of 10-bit read if an msb register is read first, it ? s corresponding lsb register is not locked thus leaving the user with the option of just reading back 8 bits (msb) of a 10-bit conversion result. reading an msb register first does not lock up other msb registers and likewise reading an lsb register first does not lock up other lsb registers. table 6. list of ADT7316/7317/7318 registers rd/wr name power-on address default 00h interrupt status 1 00h 01h interrupt status 2 00h 02h reserved 03h internal temp & v dd lsbs 00h 04h external temp lsbs 00h 05h reserved 06h v dd msbs 00h 07h internal temperature msbs 00h 08h external temp msbs 00h 09h-0fh reserved 10h dac a lsbs (ADT7316/17 only) 00h 11h dac a msbs 00h 12h dac b lsbs (ADT7316/17 only) 00h 13h dac b msbs 00h 14h dac c lsbs (ADT7316/17 only) 00h 15h dac c msbs 00h 16h dac d lsbs (ADT7316/17 only) 00h 17h dac d msbs 00h 18h control config 1 00h 19h control config 2 00h 1ah control config 3 00h 1bh dac config 00h 1ch ldac config 00h 1dh interrupt mask 1 00h 1eh interrput mask 2 00h 1fh internal temp offset 00h 20h external temp offset 00h 21h internal analog temp offset d8h
ADT7316/7317/7318 ? 21 ? re v . p r n preliminary technical data 22h external analog temp offset d8h 23h v dd v high limit c9h 24h v dd v low limit 62h 25h internal t high limit 64h 26h internal t low limit c9h 27h external t high ffh 28h external t low 00h 29h-4ch reserved 4dh device id 01h/05h/09h 4eh manufacturer ? s id 41h 4fh silicon revision 00h 50h-ffh reserved interrupt status 1 register (read only) [add. = 00h] this 8-bit read only register reflects the status of some of the interrupts that can cause the interrupt pin to go active. this register is reset by a read operation or by a software reset. table 7. interrupt status 1 register d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a 0* 0* 0* 0* 0* *default settings at power-up. bit function d 0 1 when internal temp value exceeds t high limit d 1 1 when internal temp value exceeds t low limit d 2 1 when external temp value exceeds t high limit d 3 1 when external temp value exceeds t low limit d 4 1 indicates a fault (open or short) for the external temperature sensor. interrupt status 2 register (read only) [add. = 01h] this 8-bit read only register reflects the status of the v dd interrupt that can cause the interrupt pin to go ac- tive. this register is reset by a read operation or by a soft- ware reset. table 8. interrupt status 1 register d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a 0* n/a n/a n/a n/a *default settings at power-up. bit function d 4 1 when v dd value exceeds corrosponding v high and v low limits internal temperature value/v dd value reg- ister lsbs (read only) [add. = 03h] this internal temperature value and v dd value register is a 8-bit read-only register. it stores the two lsbs of the 10-bit temperature reading from the internal temperature sensor and also the two lsbs of the 10-bit supply voltage reading. table 9. internal temp/v dd lsbs d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a n/a v1 lsb t1 lsb n/a n/a n/a n/a 0* 0* 0* 0* *default settings at power-up. bit function d 0 lsb of internal temperature value d 1 b1 of internal temperature value d 2 lsb of v dd value d 3 b1 of v dd value external temperature value register lsbs (read only) [add. = 04h] this external temperature value is a 8-bit read-only register. it stores the two lsbs of the 10-bit temperature reading from the external temperature sensor. table 10. external temperature lsbs d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a n/a n/a n/a t1 lsb n/a n/a n/a n/a n/a n/a 0* 0* *default settings at power-up. bit function d0 lsb of external temperature value d 1 b1 of external temperature value v dd value register msbs (read only) [add. = 06h] this 8-bit read only register stores the supply voltage value. the 8 msbs of the 10-bit value are stored in this register. table 11. v dd value msbs
? 22 ? re v . p r n preliminary technical data ADT7316/7317/7318 d7 d6 d5 d4 d3 d2 d1 d0 v9 v8 v7 v6 v5 v4 v3 v2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. internal temperature value register msbs (read only) [add. = 07h] this 8-bit read only register stores the internal tempera- ture value from the internal temperature sensor in twos complement format. the 8 msbs of the 10-bit value are stored in this register. table 12. internal temperature value msbs d7 d6 d5 d4 d3 d2 d1 d0 t9 t8 t7 t6 t5 t4 t3 t2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. external temperature value register msbs (read only) [add. = 08h] this 8-bit read only register stores the external tempera- ture value from the external temperature sensor in twos complement format. the 8 msbs of the 10-bit value are stored in this register. table 13. external temperature value msbs d7 d6 d5 d4 d3 d2 d1 d0 t9 t8 t7 t6 t5 t4 t3 t2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. dac a register lsbs (read/write) [add. = 10h] this 8-bit read/write register contains the 4/2 lsbs of the ADT7316/7317 dac a word respectivily. the value in this register is combined with the value in the dac a register msbs and converted to an analog voltage on the v out a pin. on power-up the voltage output on the v out a pin is 0 v. table 14. dac a (ADT7316) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b3 b2 b1 lsb n/a n/a n/a n/a 0* 0* 0* 0* n/a n/a n/a n/a *default settings at power-up. table 15. dac a (adt7317) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b2 lsb n/a n/a n/a n/a n/a n/a 0* 0* n/a n/a n/a n/a n/a n/a *default settings at power-up. dac a register msbs (read/write) [add. = 11h] this 8-bit read/write register contains the 8 msbs of the dac a word. the value in this register is combined with the value in the dac a register lsbs and converted to an analog voltage on the v out a pin. on power-up the voltage output on the v out a pin is 0 v. table 16. dac a msbs d7 d6 d5 d4 d3 d2 d1 d0 msb b8 b7 b6 b5 b4 b3 b2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. dac b register lsbs (read/write) [add. = 12h] this 8-bit read/write register contains the 4/2 lsbs of the ADT7316/7317 dac b word respectivily. the value in this register is combined with the value in the dac b register msbs and converted to an analog voltage on the v out b pin. on power-up the voltage output on the v out b pin is 0 v. table 17. dac b (ADT7316) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b3 b2 b1 lsb n/a n/a n/a n/a 0* 0* 0* 0* n/a n/a n/a n/a *default settings at power-up. table 18. dac b (adt7317) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b2 lsb n/a n/a n/a n/a n/a n/a 0* 0* n/a n/a n/a n/a n/a n/a *default settings at power-up. dac b register msbs (read/write) [add. = 13h] this 8-bit read/write register contains the 8 msbs of the dac b word. the value in this register is combined with the value in the dac b register lsbs and converted to an analog voltage on the v out b pin. on power-up the voltage output on the v out b pin is 0 v. table 19. dac b msbs d7 d6 d5 d4 d3 d2 d1 d0 msb b8 b7 b6 b5 b4 b3 b2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. dac c register lsbs (read/write) [add. = 14h] this 8-bit read/write register contains the 4/2 lsbs of the ADT7316/7317 dac c word respectivily. the value in this register is combined with the value in the dac c register msbs and converted to an analog voltage on the v out c pin. on power-up the voltage output on the v out c pin is 0 v.
ADT7316/7317/7318 ? 23 ? re v . p r n preliminary technical data table 20. dac c (ADT7316) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b3 b2 b1 lsb n/a n/a n/a n/a 0* 0* 0* 0* n/a n/a n/a n/a *default settings at power-up. table 21. dac c (adt7317) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b2 lsb n/a n/a n/a n/a n/a n/a 0* 0* n/a n/a n/a n/a n/a n/a *default settings at power-up. dac c register msbs (read/write) [add. = 15h] this 8-bit read/write register contains the 8 msbs of the dac c word. the value in this register is combined with the value in the dac c register lsbs and converted to an analog voltage on the v out c pin. on power-up the voltage output on the v out c pin is 0 v. table 22. dac c msbs d7 d6 d5 d4 d3 d2 d1 d0 msb b8 b7 b6 b5 b4 b3 b2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. dac d register lsbs (read/write) [add. = 16h] this 8-bit read/write register contains the 4/2 lsbs of the ADT7316/7317 dac d word respectivily. the value in this register is combined with the value in the dac d register msbs and converted to an analog voltage on the v out d pin. on power-up the voltage output on the v out d pin is 0 v. table 23. dac d (ADT7316) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b3 b2 b1 lsb n/a n/a n/a n/a 0* 0* 0* 0* n/a n/a n/a n/a *default settings at power-up. table 24. dac d (adt7317) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b2 lsb n/a n/a n/a n/a n/a n/a 0* 0* n/a n/a n/a n/a n/a n/a *default settings at power-up. dac d register msbs (read/write) [add. = 17h] this 8-bit read/write register contains the 8 msbs of the dac d word. the value in this register is combined with the value in the dac d register lsbs and converted to an analog voltage on the v out d pin. on power-up the voltage output on the v out d pin is 0 v. table 25. dac d msbs d7 d6 d5 d4 d3 d2 d1 d0 msb b8 b7 b6 b5 b4 b3 b2 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. control configuration 1 register (read/ write) [add. = 18h] this configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7316/17/18. table 26. control configuration 1 d7 d6 d5 d4 d3 d2 d1 d0 pd c6 c5 c4 c3 c2 c1 c0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function c0 this bit enables/disables conversions in round robin mode. ADT7316/17/18 powers up in round robin mode but monitoring is not initi- ated until this bit is set. default = 0. 0 = disable round robin monitoring. 1 = enable round robin monitoring. c1:4 reserved. only write 0 ? s. c5 0 enable interrupt 1 disable interrupt c6 configures interrupt output polarity. 0 active low 1 active high c7 power-down bit. setting this bit to 1 puts the ADT7316/17/18 into standby mode. in this mode both adc and dacs are fully powered down, but serial interface is still operational. to power up the part again just write 0 to this bit . control configuration 2 register (read/ write) [add. = 19h] this configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7316/17/18. table 27. control configuration 2 d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function
? 24 ? re v . p r n preliminary technical data ADT7316/7317/7318 c2:0 in sin gle channel mode these bits select between v dd , the internal temperature sensor and the external temperature sensor for conversion. de- fault is v dd . 000 = v dd 001 = internal temperature sensor. 010 = external temperature sensor 011 - 111 = reserved c3 reserved c4 selects between single channel and round robin conversion cycle. default is round robin. 0 = round robin. 1 = single channel. c5 default condition is to average every measure- ment on all channels 16 times. this bit disables this averaging. channels consist of temperature, analog inputs and v dd . 0 = enable averaging. 1 = disable averaging. c6 smbus timeout on the serial clock puts a max limit on the pulse width of the clock. ensures that a fault on the master scl does not lock up the sda line. 0 = disable smbus timeout. 1 = enable smbus timeout. c7 software reset. setting this bit to a 1 causes a software reset. all registers and dac outputs will reset to their default settings. control configuration 3 register (read/ write) [add. = 1ah] this configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7316/17/18. table 28. control configuration 3 d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function c0 selects between fast and normal adc conver- sion speeds for all three monitoring channels. 0 = adc clock at 1.4 khz. 1 = adc clock at 22.5 khz. c1 on the ADT7316 and adt7317, this bit selects between 8 bits and 10 bits dac output resolu- tion on the thermal voltage output feature. default = 8 bits. this bit has no affect on the adt7318 output as this part has only an 8-bit dac. in the adt7318 case, write 0 to this bit. 0 = 8 bits resolution. 1 = 10 bits resolution. c2 reserved. only write 0 ? s. c 3 0 = pin controls updating of dac out- puts. 1 = dac configration register and ldac con- figuration register control updating of dac outputs. c4 reserved. only write 0. c5 setting this bit selects dac a voltage output to be proportional to the internal temperature mea- surement. c6 setting this bit selects dac b voltage output to be proportional to the external temperature mea- surement. c7 reserved. only write 0. dac configuration register (read/write) [add. = 1bh] this configuration register is an 8-bit read/write register that is used to control the output ranges of all four dacs and also to control the loading of the dac registers if the pin is disabled (bit c3 = 1, control configuration 3 register). table 29. dac configuration d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function d 0 selects the output range of dac a. 0 = 0 v to v ref . 1 = 0 v to 2v ref . d 1 selects the output range of dac b. 0 = 0 v to v ref . 1 = 0 v to 2v ref . d 2 selects the output range of dac c. 0 = 0 v to v ref . 1 = 0 v to 2v ref . d 3 selects the output range of dac d. 0 = 0 v to v ref . 1 = 0 v to 2v ref . d5:d4 00 msb write to any dac register generates ldac command which updates that dac only. 01 msb write to dac b or dac d register generates ldac command which up- dates dacs a, b or dacs c, d. 10 msb write to dac d register generates ldac command which updates all 4 dacs. 11 ldac command generated from ldac register.
ADT7316/7317/7318 ? 25 ? re v . p r n preliminary technical data d 6 setting this bit allows the external v ref to bypass the reference buffer when supplying dacs a and b. d 7 setting this bit allows the external v ref to bypass the reference buffer when supplying dacs c and d. ldac configuration register (write only) [add. = 1ch] this configuration register is an 8-bit write register that is used to control the updating of the quad dac outputs if the pin is disabled and bits 4 and 5 of dac con- figuration register are both set to 1. also selects v ref for all four dacs. all of the bits in this register are self clear- ing i.e. reading back from this register will always give 0 ? s. table 30. ldac configuration d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function d 0 writing a 1 to this bit will generate the ldac command to update dac a output only. d 1 writing a 1 to this bit will generate the ldac command to update dac b output only. d 2 writing a 1 to this bit will generate the ldac command to update dac c output only. d 3 writing a 1 to this bit will generate the ldac command to update dac d output only. d 4 selects either internal or external v ref ab for dacs a and b. 0 = external v ref 1 = internal v ref d 5 selects either internal or external v ref cd for dacs c and d. 0 = external v ref 1 = internal v ref d6:d7 reserved. only write 0 ? s. interrupt mask 1 register (read/write) [add. = 1dh] this mask register is an 8-bit read/write register that can be used to mask out any interrupts that can can cause the interrupt pin to go active. table 31. interrupt mask 1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function d 0 0 = enable internal t high interrupt. 1 = disable internal t high interrupt. d 1 0 = enable internal t low interrupt. 1 = disable internal t low interrupt. d 2 0 = enable external t high interrupt. 1 = disable external t high interrupt. d 3 0 = enable external t low interrupt. 1 = disable external t low interrupt. d 4 0 = enable external temperature fault interrupt. 1 = disable external temperature fault interrupt. d5:d7 reserved. only write 0 ? s. interrupt mask 2 register (read/write) [add. = 1eh] this mask register is an 8-bit read/write register that can be used to mask out any interrupts that can can cause the interrupt pin to go active. table 32. interrupt mask 2 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. bit function d0:d3 reserved. only write 0 ? s. d 4 0 = enable v dd interrupts. 1 = disable v dd interrupts. d5:d7 reserved. only write 0 ? s. internal temperature offset register (read/write) [add. = 1fh] this register contains the offset value for the internal temperature channel. a 2's complement number can be written to this register which is then 'added' to the mea- sured result before it is stored or compared to limits. in this way a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. as it is an 8-bit register the temperature resolu- tion is 1 o c. table 33. internal temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up.
? 26 ? re v . p r n preliminary technical data ADT7316/7317/7318 external temperature offset register (read/write) [add. = 20h] this register contains the offset value for the internal temperature channel. a 2's complement number can be written to this register which is then 'added' to the mea- sured result before it is stored or compared to limits. in this way a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. as it is an 8-bit register the temperature resolu- tion is 1 o c. table 34. external temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. internal analog temperature offset register (read/write) [add. = 21h] this register contains the offset value for the internal thermal voltage output. a 2's complement number can be written to this register which is then 'added' to the mea- sured result before it is converted by dac a. varying the value in this register has the affect of varying the tempera- ture span. for example, the output voltage can represent a temperature span of -128 o c to +127 o c or even 0 o c to +127 o c. in essence this register changes the position of 0v on the temperature scale. anything other than -128 o c to +127 o c will produce an upper deadband on the dac a output. as it is an 8-bit register the temperature resolution is 1 o c. default value is -40 o c. table 35. internal analog temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 1* 1* 0* 0* 0* *default settings at power-up. external analog temperature offset register (read/write)[add. = 22h] this register contains the offset value for the external thermal voltage output. a 2's complement number can be written to this register which is then 'added' to the mea- sured result before it is converted by dac b. varying the value in this register has the affect of varying the tempera- ture span. for example, the output voltage can represent a temperature span of -128 o c to +127 o c or even 0 o c to +127 o c. in essence this register changes the position of 0v on the temperature scale. anything other than -128 o c to +127 o c will produce an upper deadband on the dac b output. as it is an 8-bit register the temperature resolution is 1 o c. default value is -40 o c. table 36. external analog temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 1* 1* 0* 0* 0* *default settings at power-up. v dd v high limit register (read/write) [add. = 23h] this limit register is an 8-bit read/write register which stores the v dd upper limit that will cause an interrupt and activate the interrupt output (if enabled). for this to happen the measured v dd value has to be greater than the value in this register. default value is 5.5 v. table 37. v dd v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 0* 1* 0* 0* 1* *default settings at power-up. v dd v low limit register (read/write) [add. = 24h] this limit register is an 8-bit read/write register which stores the v dd lower limit that will cause an interrupt and activate the interrupt output (if enabled). for this to happen the measured v dd value has to be less than the value in this register. default value is 2.7 v. table 38. v dd v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 1* 1* 0* 0* 0* 1* 0* *default settings at power-up. internal t high limit register (read/write) [add. = 25h] this limit register is an 8-bit read/write register which stores the 2 ? s complement of the internal temperature upper limit that will cause an interrupt and activate the interrupt output (if enabled). for this to happen the measured internal temperature value has to be greater than the value in this register. as it is an 8-bit register the temperature resolution is 1 o c. default value is +100 o c. table 39. internal t high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 1* 1* 0* 0* 1* 0* 0* *default settings at power-up. internal t low limit register (read/write) [add. 26h] this limit register is an 8-bit read/write register which stores the 2 ? s complement of the internal temperature lower limit that will cause an interrupt and activate the interrupt output (if enabled). for this to happen the measured internal temperature value has to be more
ADT7316/7317/7318 ? 27 ? re v . p r n preliminary technical data negative than the value in this register. as it is an 8-bit register the temperature resolution is 1 o c. default value is -55 o c. table 40. internal t low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 0* 1* 0* 0* 1* *default settings at power-up. external t high limit register (read/write) [add. = 27h] if pins 7 and 8 are configured for the external temperature sensor then this limit register is an 8-bit read/write regis- ter which stores the 2 ? s complement of the external tem- perature upper limit that will cause an interrupt and activate the interrupt output (if enabled). for this to happen the measured external temperature value has to be greater than the value in this register. as it is an 8-bit register the temperature resolution is 1 o c. table 41. external t high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* *default settings at power-up. external t low limit register (read/write) [add. = 28h] if pins 7 and 8 are configured for the external temperature sensor then this limit register is an 8-bit read/write regis- ter which stores the 2 ? s complement of the external tem- perature lower limit that will cause an interrupt and activate the interrupt output (if enabled). for this to happen the measured external temperature value has to be more negative than the value in this register. as it is an 8-bit register the temperature resolution is 1 o c. table 42. external t low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 r/ 1 scl sda 0 0 1 a2a1a0 p7p6p5p4p3p2p1 p0 ack. by ADT7316/17/18 stop by master start by master fr a me 1 serial bus a ddress byte frame 2 address pointer register byte 191 ack. by ADT7316/17/18 9 r/ 1 scl sda 0 0 1 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 ack. by ADT7316/17/18 start by master frame 1 serial bus address b yte frame 2 address pointer r egister byte 191 ack. by ADT7316/17/18 9 d7 d6 d5 d4 d3 d2 d1 d0 ack. by ADT7316/17/18 stop by master fra me 3 data byte 19 scl (continued) sda (continued) figure 18. i 2 c - writing to the address pointer register followed by a single byte of data to the selected register figure 17. i 2 c - writing to the address pointer register to select a register for a subsequent read operation
? 28 ? re v . p r n preliminary technical data ADT7316/7317/7318 0* 0* 0* 0* 0* 0* 0* 0* *default settings at power-up. device id register (read only) [add. = 4dh] this 8-bit read only register indicates which part the de- vice is in the model range. ADT7316 = 01h, adt7317 = 05h and adt7318 = 09h. manufacturer?s id register (read only) [add. = 4eh] this register contains the manufacturers identification number. adi ? s is 41h. silicon revision register (read only) [add. = 4fh] this register is divided into the four lsbs representing the stepping and the four msbs representing the version. the stepping contains the manufacturers code for minor revi- sions or steppings to the silicon. the version is the ADT7316/17/18 version number. the ADT7316/17/18 ? s version number is 0000b. ADT7316/7317/7318 serial interface there are two serial interfaces that can be used on this part, i 2 c and spi. a valid serial communication protocol selects the type of interface. serial interface selection the line controls the selection between i 2 c and spi. if is held high during a valid i 2 c communication then the serial interface selects the i 2 c mode once the correct serial bus address has been recognised. to set the interface to spi mode the line must be low during a valid spi communication. this will cause the interface to select the spi mode once the correct read or write command has been recognised. as per most spi standards the line must be low during every spi com- munication to the ADT7316/17/18 and high all other times. figure 20. spi - writing to the address pointer register followed by a single byte of data to the selected register d7 d6 d5 d4 d3 d2 d1 d0 data byte 18 d in (continued) scl k (continued) cs (continued) d7 scl k d in d6 d5 d4 d3 d2 d1 d6 d5 d4 d3 d2 d1 d0 sta rt write command register address 18 1 8 cs d0 d7 sda no ack. by master start by master fra m e 1 serial bus address byte fra me 2 single data byte from ADT7316/17/18 ack. by ADT7316/17/18 191 9 d7 d6 d5 d4 d3 d2 d1 d0 r/ a0a1 a2 101 scl stop by master 0 figure 19. i 2 c - reading a single byte of data from a selected register
ADT7316/7317/7318 ? 29 ? re v . p r n preliminary technical data the following sections describe in detail how to use these interfaces. i 2 c serial interface like all i 2 c-compatible devices, the ADT7316/7317/7318 has an 7-bit serial address. the four msbs of this address for the ADT7316/7317/7318 are set to 1001. the three lsbs are set by pin 11, add. the add pin can be con- figured three ways to give three different address options; low, floating and high. setting the add pin low gives a serial bus address of 1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011. there is a programmable smbus timout. when this is enabled the smbus will timeout after 25 ms of no activity. to enable it, set bit 6 of control configuration 2 regis- ter. the power-up default is with the smbus timeout disabled. the ADT7316/17/18 supports smbus packet error checking (pec) and it ? s use is optional. it is triggered by supplying the extra clocks for the pec byte. the pec is calculated using crc-8. the frame clock sequence (fcs) conforms to crc-8 by the polynominal : c(x) = x 8 + x 2 + x 1 + 1 consult smbus specification for more information. the serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high to low transition on the serial data line sda whilst the serial clock line scl remains high. this indicates that an address/data stream will follow. all slave peripherals connected to the serial bus respond to the start condition, and shift in the next 8 bits, consisting of a 7-bit address (msb first) plus a r/ bit, which determines the direc- tion of the data transfer, i.e. whether data will be writ- ten to or read from the slave device. the peripheral whose address corresponds to the trans- mitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus now remain idle whilst the selected device waits for data to be read from or written to it. if the r/ bit is a 0 then the master will write to the slave device. if the r/ bit is a 1 the master will read from the slave de- vice. 2. data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an acknowledge bit from the receiver of data. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be inter- preted as a stop signal. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master will pull the data line high during the 10th clock pulse to assert a stop condition. in read mode, the mas- ter device will pull the data line high during the low period before the 9th clock pulse. this is known as no acknowledge. the master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of opera- tion is determined at the beginning and cannot subse- quently be changed without starting a new operation. writing to the ADT7316/7317/7318 depending on the register being written to, there are two different writes for the ADT7316/7317/7318. it is not possible to do a block write to this part i.e no i 2 c auto- increment. writing to the address pointer register for a subsequent read. in order to read data from a particular register, the ad- dress pointer register must contain the address of that register. if it does not, the correct address must be written to the address pointer register by performing a single- byte write operation, as shown in figure 17. the write operation consists of the serial bus address followed by the address pointer byte. no data is written to any of the data registers. a read operation is then performed to read the register. figure 21. spi - writing to the address pointer register to select a register for a subsequent read operation d7 scl k d in d6 d5 d4 d3 d2 d1 d6 d5 d4 d3 d2 d1 d0 start write command register address 18 1 8 cs d0 d7 stop
? 30 ? re v . p r n preliminary technical data ADT7316/7317/7318 writing data to a register. all registers are 8-bit registers so only one byte of data can be written to each register. writing a single byte of data to one of these read/write registers consists of the serial bus address, the data register address written to the address pointer register, followed by the data byte written to the selected data register. this is illustrated in figure 18. to write to a different register, another start or repeated start is required. if more than one byte of data is sent in one communication operation, the ad- dressed register will be repeately loaded until the last data byte has been sent. reading data from the ADT7316/7317/7318 reading data from the adt7516/7517/7518 is done in a one byte operation. reading back the contents of a register is shown in figure 19. the register address previously figure 23. spi - reading a two bytes of data from two sequential registers figure 22. spi - reading a single byte of data from a selected register d7 d in d6 d5 d4 d3 d2 d1 x x xx x x x d0 x sclk sta rt read command data byte 1 18 1 8 cs xd out xx x x x x d6d5d4d3d2d1d0 xd7 stop d7 d in d6 d5 d4 d3 d2 d1 x x xx x x x d0 x sclk start read command data byte 1 18 1 8 cs xd out xx x x x x d6d5d4d3d2d1d0 xd7 stop data byte 2 xxxxxxxx d in (continued) 1 8 sclk (continued) cs (continued) d7 d6 d5 d4 d3 d2 d1 d0 d out (continued) having been set up by a single byte write operation to the address pointer register. if you want to read from another register then you will have to write to the address pointer register again to set up the relevant register address. thus block reads are not possible i.e. no i 2 c auto-increment. spi serial interface the spi serial interface of the ADT7316/7317/7318 con- sists of four wires, , sclk, din and dout. the is used to select the device when more than one device is connected to the serial clock and data lines. the sclk is used to clock data in and out of the part. the din line is used to write to the registers and the dout line is used to read data back from the registers. the part operates in a slave mode and requires an exter- nally applied serial clock to the sclk input. the serial
ADT7316/7317/7318 ? 31 ? re v . p r n preliminary technical data interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. there are two types of serial operations, a read and a write. command words are used to distinguish between a read and a write operation. these command words are given in table 43. address auto-increment is possible in spi mode table 43. spi command words write read 90h (1001 0000) 91h (1001 0001) write operation figures 20 and 21 show the timing diagrams for a write operation to the ADT7316/7317/7318. data is clocked into the registers on the rising edge of sclk. when the line is high the din and dout lines are in three- state mode. only when the goes from a high to a low does the part accept any data on the din line. in spi mode the address pointer register is capable of auto- incrementing to the next register in the register map with- out having to load the address pointer register each time. in figure 20 the register address portion of the diagram gives the first register that will be written to. subsequent data bytes will be written into sequential writable registers. thus after each data byte has been written into a register, the address pointer register auto increments it ? s value to the next available register. the address pointer register will auto-increment from 00h to 3fh and will loop back to start all over again at 00h when it reaches 3fh. read operation figures 22 and 23 show the timing diagrams necessary to accomplish correct read operations. to read back from a register you first have to write to the address pointer reg- ister with the address of the register you wish to read from. this operation is shown in figure 21. figure 22 shows the procedure for reading back a single byte of data. the read command is first sent to the part during the first 8 clock cycles, during the following 8 clock cycles the data contained in the register selected by the address pointer register is outputted onto the dout line. data is outputted onto the dout line on the falling edge of sclk. figure 23 shows the procedure when reading data from two sequential registers. multiple data reads are possible in spi interface mode as the address pointer register is auto-incremental. the address pointer regis- ter will auto-increment from 00h to 3fh and will loop back to start all over again at 00h when it reaches 3fh. smbus/spi interrupt the ADT7316/17/18 interrupt output is an interrupt line for devices that want to trade their ability to master for an extra pin. the ADT7316/17/18 is a slave only de- vice and uses the smbus/spi interrupt to signal the host device that it wants to talk. the smbus/spi inter- rupt on the ADT7316/17/18 is used as an over/under limit indicator. the interrupt pin has an open-drain configuration which allows the outputs of several devices to be wired- and together when the interrupt pin is active low. use d6 of the control configuration 1 register to set the active polarity of the interrupt output. the power-up default is active low. the interrupt function can be disabled or enabled by setting d5 of control configura- tion 1 register to a 1 or 0 respectively. the interrupt output becomes active when either the internal temperature value, the external temperature value or the v dd value exceed the values in their corre- sponding t high /v high or t low /v low registers. the in- terrupt output goes inactive again when a conversion result has the measured value back within the trip limits. the interrupt output requires an external pull-up resistor. this can be connected to a voltage different from v dd provided the maximum voltage rating of the inter- rupt output pin is not exceeded. the value of the pull- up resistor depends on the application, but should be as large enough to avoid excessive sink currents at the in- terrupt output, which can heat the chip and affect the temperature reading.
? 32 ? re v . p r n preliminary technical data ADT7316/7317/7318 outline dimensions (dimensions shown in inches and mm ) 16-lead qsop package ( rq-16 ) 16 9 8 1 0.19 7 (5.00) 0.18 9 (4.80) 0.24 4 (6.20) 0.22 8 (5.79) pin 1 0.157 (3.99) 0.150 (3.81) seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.059 (1.50) max 0.069 (1.75) 0.053 (1.35) 0.010 (0.20) 0.007 (0.18) 8 o 0 o

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